1. Field of the Invention
The present invention relates to an electronic system and, more particularly, to a buffer circuit that utilizes a pre-charge coupling circuit and a capacitively coupled feedforward signal to reduce the propagation delay within the buffer.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art or conventional by virtue of their inclusion within this section.
Electronic systems often use buffer circuits to receive external signals and convert those signals to appropriate voltage levels. Buffer circuits are often found in sequential electronic systems, such as those that use a regular and periodic clocking signal. Therefore, a buffer circuit can be used to receive an external clocking signal, and convert the clocking signal to an appropriate voltage level at an appropriate time. Buffer circuits preferably exhibit short delay time, often referred to as propagation delay, small skew, and low power consumption. Unfortunately, however, in order to achieve a relatively short propagation delay, most buffer circuits consume considerable power. Alternatively, the load impedance must be reduced in order to shorten propagation delay.
Increasing the power consumption by increasing current in one or more stages of a buffer circuit can reduce the charging and discharging time and, therefore, reduce propagation delay. However, the additional power consumption can be a significant penalty in the overall performance of the electronic system. Most electronic systems are constrained in the amount of power that can be consumed. Even though current might be increased to reduce propagation delay, there still remains certain intrinsic device capacitances on the various nodes of the buffer circuit which will ultimately limit propagation delay, even though power consumption is quite high.
It would be desirable to minimize propagation delay within the buffer circuit, no matter how many stages, or whether the buffer circuit utilizes differential or single-ended inputs and outputs. The desired buffer circuit having decreased propagation delay must be one that does not suffer the burden of increasing current within the buffer and the ultimate detriment of increased power consumption. Moreover, the desired buffer circuit is one that has reduced propagation delay without having to reduce the load to which the buffer circuit is connected.